1. Field of the Invention
The invention relates to ElectroStatic Discharge (ESD) protection for integrated circuits using p-well technology.
2. Prior Art
Integrated circuits are particularly susceptible to ElectroStatic Discharges (ESDs). ESDs are generated by human contact, or when handling or bonding a circuit, or merely when the part is sliding around.
The time profiles of typical ESDs (or zaps) have been studied and can be found in the literature. (C. Duvvury, C. Diaz, and T. Haddock, "Achieving Uniform nMOS Device Power Distribution For Sub-micron ESD Reliability", 1992 IEEE IEDM Proceedings, pp. 131-134).
ESDs find their way into a circuit through the metal pins which are connected to the pads through bond wires. Naturally, therefore, ways of neutralizing the harmful effects of ESDs are centered around all the contact pads of integrated circuits.
The ways of protecting an integrated circuit from ESDs depend on the function of the pin, e.g., depending on whether the pin is for input, output, or input/output (I/O) or power supply. For example, in the Duvvury reference above, a circuit is provided near the pad that works for input pins that must present high input impedance. The same circuit will not work for output or I/O pins.
ESD protection circuits are presently implemented near each pad. In a prevalent general design shown in FIG. 1, an ESD protection circuit 12 is interposed between the pad 10 and the V.sub.SS metal conduit 19. The pad is also connected to a local ESD protection circuit 13 which may further include an input buffer which is further serially connected to circuit 14. It will be appreciated that the local ESD circuit is separate from the input buffer. The metal conduit 19 can be any one of the ground, or the power supply, or the V.sub.SS conduits. The V.sub.SS conduit is usually maintained at 0 V. The function of the ESD protection circuit is to channel the charge of the ESD to the metal conduit, while not shorting out the pad 10 to the conduit 19 during regular integrated circuit operation.
In an embodiment such as the one shown in FIG. 1, the ESD protection circuit 12 comprises typically two components, one to protect against positive ESD events and one to protect against negative ESD events. In some ESD circuits, the same component protects against both negative and positive ESD events.
A generic ESD protection circuit (as shown in FIG. 1) that does not depend on whether the function of the pin is input, output or I/O would be desirable, as it would help in standardization of ESD protection circuits. The scheme of FIG. 1 is not intended to be limiting, as positive and negative ESD discharges could be channeled into voltage conduits other than that of V.sub.SS.
The generic ESD protection circuit of FIG. 1 has been utilized in the prior art. As seen in FIG. 2A, an ESD protection circuit 22 is interposed between the pad 20 and the V.sub.SS conduit 29. The ESD protection circuit 22 comprises negative and positive ESD protection circuits, and is disposed within a single p-well, in the n-type semiconductor substrate.
Protection against negative ESDs is accomplished by diode 24. During a negative ESD event, the diode 24 becomes forward biased, shorting the V.sub.SS bus to the pad. Additionally, in nMOS technology, the signals of interest are positive with respect to electrical ground. Therefore, regular input, output, and I/O signals are not affected by the diode 24.
Protection against positive ESDs is typically accomplished by grounded gate nMOS Field Effect Transistors (FETs) 25, 26, etc., arranged in parallel. While ordinary positive signals sense a high impedance between the pad 20 and the metal conduit 29, very strong signals such as those of a positive ESD event turn on FETs 25, 26, etc., and the ESD charge is therefore channeled to the metal conduit 29, instead of being channeled to the vulnerable circuit.
Accordingly, a design question is usually how many of the (usually similar) nMOS FETs or "fingers" should be disposed in parallel for the ESD protection circuit to be effective. This is a function of the rated ESD capacity of the circuit, and the material and design parameters.
However, this design approach depends on all parallel nMOS FETs working together. There is a problem that prevents them from working all together, which will be understood in terms of the following description of the invention.
General solutions have been proposed in the prior art. (See, for example, "Improving The ESD Failure Threshold Of Silicided nMOS Output Transistors By Ensuring Uniform Current Flow", T. Polgreen and A. Chatterjee, 1989 EOS/ESD Symposium Proceedings, pp. 167-174. Also, see "Achieving Uniform nMos Device Power Distribution for Submicron ESD Reliability," C. Duvvury, C. Diaz, and T. Haddock, 1992 IEEE IEDM Proceedings, pp. 131-134.) However these solutions tend to require that all parallel nMOS FETs work together, which they fail to do in the case of an ESD discharge, and in the case of the ESD circuit described in the 1992 IEEE IEDM Proceedings, this circuit can only be used for inputs (and not outputs or Input/Outputs) and this circuit requires careful design of the thick gate oxide and thin gate oxide transistors.
It would be desirable to have ESD protection structures that can be used in connection with both input and output pins. Current ESD protection structures which are multifinger arrangements of grounded gate nMOS FETs face the problem of lock-on due to snapback with subsequent burnout. Accordingly, it would be desirable to have positive ESD protection structures comprising multifinger arrangements of grounded gate nMOS FETs that all turn on simultaneously, while the burnout problem is avoided. Even though the lock-on problem usually only occurs in fabrication processes that use salicide, such processes are relatively common and thus a solution to the problem is desirable.